Interesting -- this seems to be a similar shift-amount-masking bug, but with the built-in reg extend mode that some arithmetic instructions support. Here's the relevant bit of vcode from the `RUST_LOG=debug` output: ``` Inst 111: asr x3, x3, #32 Inst 112: movz x4, #65519 Inst 113: movk x4, #65535, LSL #16 Inst 114: sub w3, w3, w4, LSL 51 ``` (The shift amount of `51` on the 32-bit `sub` is the bug.) Should be an easy fix -- will have a patch soon!
Bug 1653502 Comment 3 Edit History
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Interesting -- this seems to be a similar shift-amount-masking bug, but with the built-in reg extend/shift mode that some arithmetic instructions support. Here's the relevant bit of vcode from the `RUST_LOG=debug` output: ``` Inst 111: asr x3, x3, #32 Inst 112: movz x4, #65519 Inst 113: movk x4, #65535, LSL #16 Inst 114: sub w3, w3, w4, LSL 51 ``` (The shift amount of `51` on the 32-bit `sub` is the bug.) Should be an easy fix -- will have a patch soon!