1074102 - [meta] SIMD backend: implement SIMD operations for ARM

Status: RESOLVED WONTFIX

(Core :: JavaScript: WebAssembly, task, P5)

Description

[Douglas Crosher [:dougc]]

This bug should serve as a meta-bug for referencing all patches implementing SIMD operations for the ARM 32-bit.

Comment 1

[Douglas Crosher [:dougc]]

* We will need a solution to the current 64 bit limitation on the float register SetType. This is blocking real progress. Might be able to make some progress on the implementation of the SIMD operations without this by using some hacks and very restrictive tests.

* Early codegen results suggest we are going to need access to all 32 double float and all 16 128-bit SIMD registers for useful performance. Even the simple mandelbrot demo is full of SIMD registers spilled to the stack in the hot loop. With only 16 double float and thus 8 128-bit SIMD registers, and with one SIMD register dedicated as a scratch, there remain only 7 SIMD registers and each takes 2 double float or 4 float32 registers. Not blocking progress, but probably performance.

Comment 2

[Douglas Crosher [:dougc]]

Attachment: Hack patch to get started.

With this hack patch it is possible to run the mandelbrot asm.js demo on the ARM simulator. The SIMD codegen is not implemented so not yet emitted, but there is some plausible lowering implemented and the register allocation looks plausible. Even with this incredible hack the mandelbrot demo still runs in the browser and the non-simd code path works.

Here are the unimplemented operations needed for the mandelbrot demo:
emitFloat32X4Move
emitInt32X4Move
visitFloat32x4
visitInt32x4
visitSimdBinaryArithFx4 Add
visitSimdBinaryArithFx4 Mul
visitSimdBinaryArithFx4 Sub
visitSimdBinaryArithIx4 Add
visitSimdBinaryCompFx4 lessThanOrEqual
visitSimdExtractElementI
visitSimdSignMaskX4
visitSimdSplatX4 MIRType_Float32x4
visitSimdValueFloat32x4

Comment 3

[Douglas Crosher [:dougc]]

Attachment: Hack patch to get started.

Rebase. Update for the shift operation, and add stubs for the select operation.

Comment 4

[Douglas Crosher [:dougc]]

Attachment: 1. Move the shift operation lowering into the backends.

Moved from bug 1074867. Carrying forward r+.

Comment 5

[Douglas Crosher [:dougc]]

Attachment: 2. Move the shift operation lowering into the backends.

Moved from bug 1074867. Carrying forward r+.

Comment 7

[Benjamin Bouvier [:bbouvier] (inactive)]

My hope is to get some time later to carry on this hack, to see the mandelbrot demo alive on the ARM simulator on a browser, if anybody else doesn't do it before. Having the mandelbrot demo working with this hack would be very helpful for generalizing regalloc / typeregistersets.

Comment 8

[Douglas Crosher [:dougc]]

Attachment: 1. Move the insert-element lowering into the backends.

Rebase. Carry forward r+.

Comment 9

[Douglas Crosher [:dougc]]

Attachment: 2. move the shift operation lowering into the backends.

Rebase. Carry forward r+.

Comment 10

[Douglas Crosher [:dougc]]

Attachment: 3. Hack patch to start implementing SIMD operations for ARM

Rebased. Still works with the mandelbrot demo again - it compiles and generates plausible lower and register allocation but many of the SIMD code generation methods still need to be implemented.

Comment 11

[James Willcox (:snorp) ([e-mail]) (he/him)]

We're interested in getting this into Fennec. We're tracking for 36, but understand that maybe that won't happen.

Comment 12

[Lars T Hansen [:lth]]

We have no plans as of yet to support wasm SIMD on ARM; the future (for SpiderMonkey) is ARM64.