Open Bug 1100339 Opened 5 years ago Updated 3 years ago
Remove redundant memory barriers
The current Atomics spec calls for sequential consistency of its operations, which in the case of ARM, PowerPC, and MIPS usually means emitting one ordering memory barrier before the operation and another after the operation. When two Atomics operations are performed back-to-back, two memory barrier instructions will separate the operations in the emitted code. One of those barriers is redundant, other things being equal, and can be removed. At the same time, the use of CAS loops or lock-prefixed instructions to implement some atomic binary operations hides barriers, so it's not obvious yet how much we can optimize. Actual opportunities are dictated by the shape of typical code, and we don't know that yet.
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