Closed Bug 1209873 Opened 9 years ago Closed 9 years ago

IonMonkey: MIPS: Implement memory barrier

Categories

(Core :: JavaScript Engine: JIT, defect)

Other
Linux
defect
Not set
normal

Tracking

()

RESOLVED FIXED
mozilla44
Tracking Status
firefox44 --- fixed

People

(Reporter: hev, Assigned: hev)

References

Details

Attachments

(2 files)

Implement CodeGenerator::memoryBarrier.
Thanks!
Attachment #8667748 - Flags: review?(arai.unmht)
Thanks!
Attachment #8667749 - Flags: review?(nicolas.b.pierron)
Comment on attachment 8667748 [details] [diff] [review]
0001-IonMonkey-MIPS-Add-AssemblerMIPSShared-as_sync.patch

Review of attachment 8667748 [details] [diff] [review]:
-----------------------------------------------------------------

Looks good :)
(|stype| argument might be unnecessary at this point tho)
Attachment #8667748 - Flags: review?(arai.unmht) → review+
Comment on attachment 8667749 [details] [diff] [review]
0002-IonMonkey-MIPS-Implement-memory-barrier.patch

Review of attachment 8667749 [details] [diff] [review]:
-----------------------------------------------------------------

I will forward this review to Lars, as he might know better than me.
Attachment #8667749 - Flags: review?(nicolas.b.pierron)
Attachment #8667749 - Flags: review?(lhansen)
Attachment #8667749 - Flags: feedback+
Comment on attachment 8667749 [details] [diff] [review]
0002-IonMonkey-MIPS-Implement-memory-barrier.patch

Review of attachment 8667749 [details] [diff] [review]:
-----------------------------------------------------------------

r+, but I'd really like to see as_sync(16) now and a followup bug for other optimizations.

::: js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
@@ +1507,5 @@
> +void
> +CodeGeneratorMIPSShared::memoryBarrier(MemoryBarrierBits barrier)
> +{
> +    if (barrier)
> +      masm.as_sync();

This is correct as it stands, but:

* It should be as_sync(16), as all you need is an ordering barrier, not a completion barrier, which is potentially much more expensive.

* You probably should also distinguish between the different barrier needs by inspecting the barrierBits.  If the barrier is only LoadLoad then you could emit as_sync(19), cf the MIPS manual and the ARM code.

But that last point is an optimization and it's fine with me if you file a followup bug for "barrier optimization" or something like that, referencing these observations.
Attachment #8667749 - Flags: review?(lhansen) → review+
Blocks: 1209962
https://hg.mozilla.org/mozilla-central/rev/480c75fccf40
https://hg.mozilla.org/mozilla-central/rev/c57050c5e021
Status: ASSIGNED → RESOLVED
Closed: 9 years ago
Resolution: --- → FIXED
Target Milestone: --- → mozilla44
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