1259975 - Determine why layer borders are different during TPS run between e10s and non-e10s

Status: RESOLVED WONTFIX

(Core :: Graphics: Layers, defect)

Description

[Mike Conley (:mconley) (:⚙️)]

Attachment: e10s

I turned on layer borders and used apitrace to get a dump of what was sent to the GPU. It looks like for at least some pages, the layers are organized slightly differently. Is this difference in organization expected? Could this impact performance?

Comment 1

[Mike Conley (:mconley) (:⚙️)]

Attachment: non-e10s

Comment 2

[Mike Conley (:mconley) (:⚙️)]

Hey Jeff, anything to be concerned about regarding this discrepancy between e10s and non-e10s?

Comment 3

[Benoit Girard (:BenWa)]

(In reply to Mike Conley (:mconley) - Needinfo me! from comment #0)
> Is this difference in organization expected?

Hard to say off-hand but it shouldn't be too hard to find out what's causing it. Certainly very interesting.

> Could this impact performance?

Yes. Ideally it should only make a different in the single digit ms if that's what we're after. Probably worth having a look. I can take a look on Monday if no one else knows.

Comment 4

[Benoit Girard (:BenWa)]

Can you post both about:support as a sanity check?

Comment 5

[Benoit Girard (:BenWa)]

We discussed this in person. Layer differences are expected since the display-port is of a different size. This leads to a different display list and layer construction.

Comment 6

[Mike Conley (:mconley) (:⚙️)]

Wait a second - aren't we doing display port suppression from the work in bug 1186662? Why are the displayports different sizes?

Comment 7

[Benoit Girard (:BenWa)]

I left out reasons in Comment 5. Event region and APZ also affect the layer decisions.