Closed Bug 1294321 Opened 5 years ago Closed 5 years ago

IonMonkey: MIPS: Import Loongson optimizations to ma_ss and ma_sd baseindex

Categories

(Core :: JavaScript Engine: JIT, defect)

Other
Linux
defect
Not set
normal

Tracking

()

RESOLVED FIXED
mozilla51
Tracking Status
firefox51 --- fixed

People

(Reporter: hev, Assigned: hev)

Details

Attachments

(1 file)

Same as Bug 1293606, but this is for floating-point store.

1. MacroAssemblerMIPSShared::ma_sd(FloatRegister ft, BaseIndex address)
2. MacroAssemblerMIPSShared::ma_ss(FloatRegister ft, BaseIndex address)

Loongson instructions specs:
==== gsswxc1 - Store Word Indexed from Floating Point ====

31      26 25      21 20     16 15       11 10       3 2     0
SDC2      |   base   |    fs   |   index   |  offset  |  WORD
111110                                                   110

Format: GSSWXC1	fs, offset(base, index)
To store a word from an FPR to memory (GPR + GPR addressing)

Description: memory[GPR[base] + GPR[index] + offset] <--- FPR[fs]
The low 32-bit word from FRP fs is stored in memory at the location specified by the aligned effective address. The contents of GPR index and GPR base and IMM offset are added to form the effective address.

Restrictions:
An address Error exception occurs if EffectiveAddress[bit1..bit0] != 0 (not word-aligned).

Exceptions:
TLB Refill, TLB Invalid, TLB Modified, Address Error, Reserved Instruction, Coprocessor Unusable, Watch


==== gssdxc1 - Store Doubleword Indexed from Floating Point ====

31      26 25      21 20     16 15       11 10       3 2     0
SDC2      |   base   |    fs   |   index   |  offset  |  DWORD
111110                                                   111

Format: GSSDXC1	fs, offset(base, index)
To store a doubleword from an FPR to memory (GPR + GPR addressing)

Description: memory[GPR[base] + GPR[index] + offset] <--- FPR[fs]
The low 64-bit word from FRP fs is stored in memory at the location specified by the aligned effective address. The contents of GPR index and GPR base and IMM offset are added to form the effective address.

Restrictions:
An address Error exception occurs if EffectiveAddress[bit2..bit0] != 0 (not word-aligned).

Exceptions:
TLB Refill, TLB Invalid, TLB Modified, Address Error, Reserved Instruction, Coprocessor Unusable, Watch
Thank you.
Attachment #8779961 - Flags: review?(arai.unmht)
Attachment #8779961 - Flags: review?(arai.unmht) → review+
Pushed by r@hev.cc:
https://hg.mozilla.org/integration/mozilla-inbound/rev/422dd7521fa3
IonMonkey: MIPS: Import Loongson optimizations to ma_ss and ma_sd baseindex. r=arai
https://hg.mozilla.org/mozilla-central/rev/422dd7521fa3
Status: ASSIGNED → RESOLVED
Closed: 5 years ago
Resolution: --- → FIXED
Target Milestone: --- → mozilla51
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