1298334 - IonMonkey: MIPS64: Refactor MacroAssembler::unboxInt32

Status: RESOLVED FIXED

(Core :: JavaScript Engine: JIT, defect)

Description

[hev [:hev]]

Refactor MasmAssemblerMIPS64::unboxInt32 uses MIPS SLL instruction for MIPS64.

=== MIPS SLL Instruction ===
Format: SLL rd, rt, sa
Purpose: Shift Word Left Logical
To left-shift a word by a fixed number of bits

Description: GPR[rd] ← GPR[rt] << sa
The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeros into the emptied bits; the word
result is sign-extended and placed in GPR rd. The bit-shift amount is specified by sa.

Operation:
	s ← sa
	temp ← GPR[rt] (31-s)..0 || 0 s
	GPR[rd] ← sign_extend(temp)

Programming Notes:
Unlike nearly all other word operations, the SLL input operand does not have to be a properly sign-extended word
value to produce a valid sign-extended 32-bit result. The result word is always sign-extended into a 64-bit destination
register; this instruction with a zero shift amount truncates a 64-bit value to 32 bits and sign-extends it.

SLL r0, r0, 0, expressed as NOP, is the assembly idiom used to denote no operation.
SLL r0, r0, 1, expressed as SSNOP, is the assembly idiom used to denote no operation that causes an issue break on
superscalar processors.

Comment 1

[hev [:hev]]

Attachment: 0001-Bug-1298334-IonMonkey-MIPS64-Refactor-MacroAssembler.patch

Comment 2

[Tooru Fujisawa [:arai]]

Comment on attachment 8785763 [details] [diff] [review]
0001-Bug-1298334-IonMonkey-MIPS64-Refactor-MacroAssembler.patch

Review of attachment 8785763 [details] [diff] [review]:
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Thank you for the patch and spec :)

Comment 3

[Pulsebot]

Pushed by [e-mail]:
https://hg.mozilla.org/integration/mozilla-inbound/rev/0c9edb196d5c
IonMonkey: MIPS64: Refactor MacroAssembler::unboxInt32. r=arai

Comment 4

[Wes Kocher (:KWierso) (Not reading bugmail; email directly if needed)]

https://hg.mozilla.org/mozilla-central/rev/0c9edb196d5c