Open Bug 1330187 Opened 7 years ago Updated 1 year ago

DisplayList building shows signs of poor CPU usage

Categories

(Core :: Layout, defect, P3)

defect

Tracking

()

Performance Impact low

People

(Reporter: bas.schouten, Unassigned)

References

(Depends on 1 open bug, Blocks 1 open bug)

Details

(Keywords: perf:resource-use)

Attachments

(1 file)

Profiling indicates that DisplayList building is doing a lot of work during which the CPU is not retiring intructions but waiting for the Front-End and Back-End portions of the pipeline. During Scrolling on Google Docs, where display list building and processing takes a lot of the time, on my P50 the full 16 GB/s bandwidth of the DRAM bus is completely filled up, which is causing a lot of back, and we're seeing a large amount of instruction cache misses as well as a high ITLB overhead. This is likely because of accessing a lot of functions which are far apart in memory, as well as accessing a lot of objects in memory in suboptimal order. These seem to be the areas we should focus on when trying to improve display list building and processing performance.
Blocks: 1204549
More readable and better profile data.
Depends on: 1330558
Depends on: 1330570
Depends on: 1331718
Depends on: 1331928
Priority: -- → P3
Performance Impact: --- → ?
Performance Impact: ? → P3
Severity: normal → S3
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