1412030 - [MIPS] Emit wasm memory access information

Status: RESOLVED FIXED

(Core :: JavaScript Engine: JIT, defect)

Description

[Dragan Mladjenovic]

User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/51.0.2704.106 Safari/537.36

Steps to reproduce:

Run jit_test.py   dist/bin/js wasm/errors.js on mips32



Actual results:

Test failing.


Expected results:

Test passing.

Comment 1

[Dragan Mladjenovic]

Attachment: bug1412030.patch

Fixes CodeGenerator to emit memory access information for wasm loads and stores. Includes changes for partial writes to make first memory access to higher memory address in order to ensure that we don't get OOB trap while accessing lower memory. (see 1343981)

Comment 2

[Lars T Hansen [:lth]]

Comment on attachment 8922407 [details] [diff] [review]
bug1412030.patch

Review of attachment 8922407 [details] [diff] [review]:
-----------------------------------------------------------------

Looks plausible.  I appreciate the extra effort to get the unaligned stores right :)

::: js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
@@ +2021,5 @@
>          if (byteSize == 4) {
> +            masm.storeFloat32(value, address);
> +        } else {
> +            // For time being storeDouble for mips32 uses two store instructions,
> +            // so we emit only one to get correct beahvir in case of OOB access.behavior.

"correct behavior", and the "behavior" on the end of the line seems like it's left over from an edit.

::: js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
@@ +554,5 @@
>  {
>      int16_t lowOffset, hiOffset;
>      Register base;
>  
>      asMasm().computeScaledAddress(src, SecondScratchReg);

As a general comment (for a future patch), you should really be using ScratchRegisterScope and SecondScratchRegisterScope to allocate the scratch registers in the macroassembler, it will make it much less likely that there's a confusion about who owns these registers.

Comment 3

[Dragan Mladjenovic]

Attachment: bug1412030_2.patch

Comment 4

[Pulsebot]

Pushed by [e-mail]:
https://hg.mozilla.org/integration/mozilla-inbound/rev/db33caee757e
[MIPS] Emit wasm memory access information. r=lth

Comment 5

[Sebastian Hengst [:aryx] (needinfo me if it's about an intermittent or backout)]

https://hg.mozilla.org/mozilla-central/rev/db33caee757e