Open Bug 1653916 Opened 4 years ago Updated 4 years ago

Try to get an extra register in CacheIRCompiler

Categories

(Core :: JavaScript Engine: JIT, task, P3)

Product:
Core
Component:
JavaScript Engine: JIT
Type:
task

Tracking

()

People

(Reporter: jandem, Unassigned)

References

(Blocks 1 open bug)

Details

In CacheIRCompiler we can allocate at most 5 registers on 32-bit x86. Having access to an extra register would go a long way.

One option is to treat ICStubReg as an IC input and let the allocator spill/restore it. Then ops that don't use stub fields get access to an extra register. This could potentially also work for the frame pointer register. Another option is to improve the allocator interface somehow.

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