Closed Bug 1727112 Opened 3 months ago Closed 3 months ago

Simplify load/store temp registers in baseline compiler

Categories

(Core :: Javascript: WebAssembly, enhancement, P3)

enhancement

Tracking

()

RESOLVED FIXED
93 Branch
Tracking Status
firefox93 --- fixed

People

(Reporter: lth, Assigned: lth)

Details

Attachments

(1 file)

This is fallout from the recent cleanup of the ARM code wherein we stopped handling accesses flagged as unaligned specially. Some code was not removed but should have been, and is removed here; in turn, this reduces the needs for temp registers and the changes for that percolate into the mips64 backend too.

Remove two special cases for ARM where we tested for unaligned accesses, we do
not need to do this, as we do not treat them specially. This just created
extra register pressure.

As a result, needLoadTemps can allocate at most one temp (on MIPS), and the
load() function takes at most one temp since ARM no longer needs any temps.
So simplify all paths by removing the always-dead second and third temps.

Now needLoadTemps and needStoreTemps are MIPS-only and very simple, so
inline them in their unique callers.

Pushed by lhansen@mozilla.com:
https://hg.mozilla.org/integration/autoland/rev/881b74a21041
Simplify load/store temp regs in baseline. r=jseward
Status: ASSIGNED → RESOLVED
Closed: 3 months ago
Resolution: --- → FIXED
Target Milestone: --- → 93 Branch
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