455588 - Merge tracemonkey nanojit changes into TT.

Status: VERIFIED WONTFIX

(Tamarin Graveyard :: Tracing Virtual Machine, defect)

Comment 1

[Andreas Gal :gal]

Attachment: Current diff against TT.

Comment 2

[Andreas Gal :gal]

David and vlad will comment on their changes separately:

- Applied the incremental cache growth patch. This breaks arm and thumb since pages can be far apart now. vlad's code compensates for this for arm. Thumb is still broken (but I think we should keep it that way for now).
- Split getLoop and newLoop and introduce peer fragments. A peer fragment is an "alternative" fragment for the same ip where we already have a fragment. This is useful for specializing code.

Comment 3

[Vladimir Vukicevic [:vlad] [:vladv] (needinfo me, slow to respond)]

For the arm stuff:

- New ARM cpp file and fixes to ARM .h; FP code etc in there, all ARM isolated.
- The ARM __clear_cache call for flushing instruction cache

Only non-arm stuff:

- In arFree, bail out early if idx == 0 (nothing to free)
- In RegAlloc, always allocate 32 regs in active array instead of NJ_MAX_REGISTERS -- otherwise, things break badly if you have holes in your register indexes (e.g. to have an easier mapping between the register enum and hw regs).  However, this should probably be undone -- the problem is only in verbose at http://mxr.mozilla.org/mozilla-central/source/js/src/nanojit/RegAlloc.cpp#136 and that should be fixed in a different way.

Comment 4

[David Anderson [:dvander] - inactive, e-mail if emergency]

I r+'d some patches from Ginn Chen:
 - Removed unnecessary of DARWIN and AVMPLUS_LINUX for AVMPLUS_UNIX
 - Added support for Sun's Solaris compiler.
 - Added FASTCALL simulation/fixes since Solaris doesn't have fastcall.

For the AMD64 backend:
 - Added support for large-range jumps (necessary for incremental code allocation).  Since AMD64 doesn't have 64-bit immediate jump offsets, it now stores the target in the page and does an indirect jump.
 - We needed a "return 64-bit integer" version of LIR_call, so on AMD64 I took LIR_callh.  We could probably have a LIR_callq instead if you preferred. 
 - Fixed register allocation bugs some of which you fixed in redux-nanojit.  For example, asm_fneg/fop needed to handle getting a GPR register; asm_load64 was missing memory-memory loads; asm_store64 and asm_quad were just wrong.
 - Added a few opcodes for 64-bit integer operations against 32-bit sign-extended integers: LIR_qiadd, LIR_qilsh, LIR_qior, LIR_qiand.
 - Fixed various bugs in the AMD64 header+macros.
 - Made asm_restore/spill always do 64-bit loads/stores for safety.
 - Added LIR_qcmov which supports one or both operands being 64-bit.  This sounds sketchy in retrospect and we no longer appear to be LIR_cmov at all, might need to be revisited.
 - Added constvalp() to decide between constval/constvalq
 - Fixed LIR far tramps being too narrow
 - Fixed portability bugs (pointers being chopped from not using intptr_t).

General changes:
 - Changed to variadic macros, shimmed in VS 7.1 support (easy to undo if necessary).
 - Added explicit deallocation everywhere since we don't GC unmanaged memory.
 - Added Fragment::onDestroy as a hook to free vmprivate.  This is a shim, looking for something nicer.
 - We now use mmap/munmap (SELinux didn't like valloc) and changed Fragmento to keep track of the sizes of each allocation it makes.

If I can remember more I'll post again.

Comment 5

[Steven Johnson]

I'll be (pleasantly) surprised if all target compilers support variadic macros. In particular, I think that current Symbian compilers don't.

Comment 6

[Edwin Smith]

(In reply to comment #5)
> I'll be (pleasantly) surprised if all target compilers support variadic macros.
> In particular, I think that current Symbian compilers don't.

Turns out, even CW does, so we should be good at least on msc/gcc/cw/armcc