(needs experimental evidence to back up this claim).
Severity: normal → minor
Priority: -- → P2
Target Milestone: --- → flash10.2
Yes and please include architecture / processor specifics with any data, as there is most likely variance amongst the chips.
x86 is the only applicable architecture, and msvc/gcc are the only applicable compilers. All other CPU types have a register rich calling convention that doesn't change for plain functions vs method calls. (and FASTCALL is an empy macro for them).
Right, I was referring to variants in x86 chip architectures that might manifest as deltas in performance. For example, dual-core vs. core2 vs Nehalem based chips; where each may exhibit slightly different effects from this change.
Target Milestone: Q3 11 - Serrano → Q1 12 - Brannan
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