Closed Bug 570694 Opened 10 years ago Closed 10 years ago
Extend the range for individual FSTD instructions on ARM
The FSTD instruction can take an 8-bit offset, but this offset is assumed to be 4-byte-aligned and effectively has a range of -1020 <= d <= 1020. The existing code in asm_store64 doesn't recognize this, and restricts the range to -255 <= d <= 255. (Extra instructions are used to implement the out-of-range case.) I think the out-of-range case barely ever turns up, but the patch to correct it is trivial.
Attachment #449837 - Flags: review?(nnethercote)
Comment on attachment 449837 [details] [diff] [review] Extend the inappropriately-limited FSTD and FSTS range. The patch looks like it does what you describe. I'll take your word that what you describe about the architecture is correct!
Whiteboard: fixed-in-nanojit → fixed-in-nanojit, fixed-in-tamarin
Status: ASSIGNED → RESOLVED
Closed: 10 years ago
Resolution: --- → FIXED
Comment on attachment 449837 [details] [diff] [review] Extend the inappropriately-limited FSTD and FSTS range. Looks like I forgot to mark the r+. Doing so now to clean out my review queue.
Attachment #449837 - Flags: review?(nnethercote) → review+
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