In-line lf32x4 and sf32x4 on little-endian platforms

NEW
Unassigned

Status

Tamarin
Baseline JIT (CodegenLIR)
P3
normal
6 years ago
6 years ago

People

(Reporter: Lars T Hansen, Unassigned)

Tracking

(Blocks: 1 bug)

unspecified
Q2 12 - Cyril

Details

(Reporter)

Description

6 years ago
Spun off from bug #706757.  The new opcodes are supported in the JIT and the interpreter but CodegenLIR should emit in-line code for them when appropriate, using SIMD load/store instructions.

The use of SIMD load/store instructions will require some work on ByteArray to guarantee that ByteArray storage is always 16-byte aligned, or the use of load/store instructions that allow unaligned access, or the use of instruction sequences (eg four back-to-back float loads).
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