1052384 - Regalloc: Generalize TypedRegisterSets

Status: RESOLVED WORKSFORME

(Core :: JavaScript Engine: JIT, defect)

Description

[Benjamin Bouvier [:bbouvier] (inactive)]

Following the conversations face to face that we've had during the Toronto work week and recent IRC / bug discussions, here is a bug whose goal is to figure out an efficient (memory and speed) way to do registers allocation. In particular, I think we need to change TypedRegisterSets.

A few requirements that went to mind:
- register aliasing needs to be taken into account, for architectures that have aliased registers (ARM, maybe MIPS?).
- we need to be able to know what's the type of the register's content (for instance: xmm0 contains a double, xmm1 contains a float32, xmm2 contains a Simd128). Thanks to this, we'll be able to specialize moves instructions (e.g. for SIMD, say we want to use movaps for float32x4 or movdqa for int32x4). 
- it needs to be efficient in speed (it's heavily used during regalloc, iirc) and in memory:
  - on ARM: FloatRegisterSet is 64 bits, GPR set is 32 bits
  - on x64: both are 32 bits
  - on x86: FloatRegisterSet is 32 bits, GPR is 8 bits

Ideas and remarks are more than welcome.

Marking as a blocker for 947711, as it blocks regalloc on ARM (well, Marty said it's not needed per se, but as I understand it, it would be very sad to augment FloatRegisterSet on ARM without thinking some more).

Comment 1

[Nicolas B. Pierron [:nbp]]

These issues got addressed as part of Bug 1143011, and were enough for implementing Bug 1112164.