1510749 - ARM64: Allow CSINC to accept WZR/XZR

Status: RESOLVED FIXED

(Core :: JavaScript Engine: JIT, enhancement, P2)

Description

[Sean Stangl [:sstangl]]

Attachment: 0001-The-AArch64-ISR-explicitly-allows-CSINC-to-accept-ZR.patch

VIXL prevents the 2nd and 3rd registers in CSINC from being WZR/XZR, but the AArch64 ISR explicitly allows that, and in fact the VIXL codegen internally calls (the assembler variant, without assertions, of) CSINC with WZR.

The assertions are commented-out instead of being deleted because the change needs to be propagated when we eventually upgrade to a recent VIXL release.

Fixes ion/bug1140890.js and a bunch of other failures.

Comment 1

[Nicolas B. Pierron [:nbp]]

Comment on attachment 9028422 [details] [diff] [review]
0001-The-AArch64-ISR-explicitly-allows-CSINC-to-accept-ZR.patch

Review of attachment 9028422 [details] [diff] [review]:
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I would add that CSET and CINC are aliases of CSINC instruction which are explicitly making use of the XZR register.

Comment 2

[Sean Stangl [:sstangl]]

Attachment: 0001-Bug-1510749-The-AArch64-ISR-explicitly-allows-CSINC-.patch

Thanks! Added comment about CSET, carrying r+.

CINC does accept WZR/XZR but isn't defined in terms of CSINC with WZR/XZR as CSET is.

Comment 3

[Pulsebot]

Pushed by [e-mail]:
https://hg.mozilla.org/integration/mozilla-inbound/rev/6c17ac872bdf
The AArch64 ISR explicitly allows CSINC to accept ZR. r=nbp

Comment 4

[Cristina Coroiu [:ccoroiu]]

https://hg.mozilla.org/mozilla-central/rev/6c17ac872bdf