Open Bug 1706106 Opened 8 months ago Updated 7 months ago

SIMD load/store lane optimizations in ARM64 Ion

Categories

(Core :: Javascript: WebAssembly, enhancement, P3)

ARM64
All
enhancement

Tracking

()

People

(Reporter: yury, Unassigned)

References

(Blocks 2 open bugs)

Details

Bug 1687629 implements Ion non-optimized operations. The current code is using temporary register to load a lane and then replace it the SIMD register (for load), and extracting lane and then storing it.

The https://github.com/WebAssembly/simd/pull/350 recommends usage of LD1 / ST1 instructions. Though there is a limit: there is not encoding for memory referred via base register value and an offset register (which we use).

Check if it is possible to optimize load/store lane operations.

Blocks: 1687630
Severity: S2 → N/A
Type: defect → enhancement
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