1987693 - riscv64: Unify 32b-to-64b int sign extension to using SignExtendWord

Status: RESOLVED FIXED

(Core :: JavaScript Engine: JIT, task, P5)

Description

[Rong Bao [:csmantle]]

Currently many equivalent instructions are used in riscv64 backend for 32b-to-64b sign extension, like slliw rx, ry, 0. However, the ISA spec recommends the usage of addiw rx, ry, 0 as a sign extension instruction, and even defines a pseudoinstruction sext.w for it:

Note, ADDIW rd, rs1, 0 writes the sign extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).

-- https://riscv.github.io/riscv-isa-manual/snapshot/unprivileged/#norm:inst:addiw:operation

And we already have a MacroAssemblerRiscv64Compat::SignExtendWord defined for it. Using this to perform sign extension would make this operation look uniform in disassembly.

Comment 1

[Rong Bao [:csmantle]]

Attachment: Bug 1987693 - [riscv64] Use MacroAssemblerRiscv64Compat::SignExtendWord for 32b-to-64b sign extension. r=jandem

Comment 2

[Pulsebot]

Pushed by [e-mail]:
https://github.com/mozilla-firefox/firefox/commit/f38a74b508e2
https://hg.mozilla.org/integration/autoland/rev/44ad01563397
[riscv64] Use MacroAssemblerRiscv64Compat::SignExtendWord for 32b-to-64b sign extension. r=jandem

Comment 3

[Serban Stanca [:SerbanS]]

https://hg.mozilla.org/mozilla-central/rev/44ad01563397