Closed Bug 1995496 Opened 1 year ago Closed 1 year ago

Use div+mod sequence on risc64

Categories

(Core :: JavaScript Engine: JIT, enhancement, P3)

enhancement

Tracking

()

RESOLVED FIXED
146 Branch
Tracking Status
firefox146 --- fixed

People

(Reporter: anba, Assigned: anba)

References

(Blocks 1 open bug)

Details

Attachments

(2 external files)

From https://riscv.github.io/riscv-isa-manual/snapshot/unprivileged/#_division_operations:

If both the quotient and remainder are required from the same division, the recommended code sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides.

From https://riscv.github.io/riscv-isa-manual/snapshot/unprivileged/#_division_operations:

If both the quotient and remainder are required from the same division, the
recommended code sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2
(rdq cannot be the same as rs1 or rs2). Microarchitectures can then
fuse these into a single divide operation instead of performing two separate
divides.

The name ma_div_branch_overflow is misleading, because there's no "overflow".
Inlining the method also makes it easier to use the recommended div-mod
sequence on riscv64.

Severity: -- → N/A
Priority: -- → P3
Status: ASSIGNED → RESOLVED
Closed: 1 year ago
Resolution: --- → FIXED
Target Milestone: --- → 146 Branch
QA Whiteboard: [qa-triage-done-c147/b146]
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