Port div/mod optimisations to riscv64
Categories
(Core :: JavaScript Engine: JIT, enhancement)
Tracking
()
| Tracking | Status | |
|---|---|---|
| firefox154 | --- | fixed |
People
(Reporter: anba, Assigned: anba)
References
(Blocks 1 open bug)
Details
Attachments
(11 external files)
- Support negative and unsigned modes for
LDivPowTwoIandLModPowTwoI. - Implement
LDivConstantIandLModConstantI(also unsigned and 64-bit versions). - Implement
LDivPowTwoI64andLModPowTwoI64.
Also see bug 1998457 for 64-bit division with constants on x64/arm64.
| Assignee | ||
Comment 1•4 months ago
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Fixes:
- Add
letto avoid creating global variables. - Fix argument order for
assertEq. - And modernise some code.
| Assignee | ||
Comment 2•4 months ago
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Add codegenTestShared_adhoc to avoid code duplication.
Used in part 10 when "codegen-riscv64-test.js" gets added.
| Assignee | ||
Comment 3•4 months ago
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The instruction decoder already emits the instruction bits.
Necessary for part 10 when checking the disassembly.
| Assignee | ||
Comment 4•4 months ago
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Update implementation to match the ARM64 code.
| Assignee | ||
Comment 5•4 months ago
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Update implementation to match the ARM64 code.
| Assignee | ||
Comment 6•4 months ago
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Implementation based on the x86-shared and arm64 code.
| Assignee | ||
Comment 7•4 months ago
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Implementation based on the x86-shared and arm64 code.
| Assignee | ||
Comment 8•4 months ago
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| Assignee | ||
Comment 9•4 months ago
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| Assignee | ||
Comment 10•4 months ago
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Tests copied from "binop-divrem-with-constant-arm64-ion-codegen.js" and then updated
for riscv64.
| Assignee | ||
Comment 11•4 months ago
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LModMaskI is no longer needed when LModConstantI is supported.
(module
(func (export "f") (param i32) (result i32)
(i32.rem_s (local.get 0) (i32.const 3))))
Was compiled to:
sext.w s1, a0
sext.w t2, s1
mv t1, t2
mv a0, zero
blt t1, zero, 12 -> L_negative
li t0, 1
j 12 -> L_head
L_negative:
li t0, -1
negw t1, t1
L_head:
andi t4, t1, 0x3
addw a0, a0, t4
addiw t4, a0, -3
blt t4, zero, 8 -> L_sum_signed
mv a0, t4
L_sum_signed:
srliw t1, t1, 2
bne t1, zero, -24 -> L_head
bge t0, zero, 8 -> L_done
negw a0, a0
L_done:
And is now compiled to the branchless code:
sext.w t1, a0
sext.w t0, t1
lui t4, 0x55555
addiw t4, t4, 1366
mul a0, t0, t4
srli a0, a0, 32
sraiw t4, t0, 31
subw a0, a0, t4
sh1add a0, a0, a0
sext.w a0, a0
subw a0, t0, a0
Comment 12•4 months ago
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Comment 13•4 months ago
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| bugherder | ||
https://hg.mozilla.org/mozilla-central/rev/0c0d2d932610
https://hg.mozilla.org/mozilla-central/rev/7faea97ce670
https://hg.mozilla.org/mozilla-central/rev/a8901b969286
https://hg.mozilla.org/mozilla-central/rev/cdb9c6e53b6a
https://hg.mozilla.org/mozilla-central/rev/93a8b8660a04
https://hg.mozilla.org/mozilla-central/rev/f715a4bf1ed7
https://hg.mozilla.org/mozilla-central/rev/50d1233f8a4b
https://hg.mozilla.org/mozilla-central/rev/76920a6ee335
https://hg.mozilla.org/mozilla-central/rev/3d482e8d164c
https://hg.mozilla.org/mozilla-central/rev/65702dfdf1a9
https://hg.mozilla.org/mozilla-central/rev/226feb018134
Updated•3 months ago
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Description
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