Closed Bug 2050735 Opened 4 months ago Closed 4 months ago

Port div/mod optimisations to riscv64

Categories

(Core :: JavaScript Engine: JIT, enhancement)

enhancement

Tracking

()

RESOLVED FIXED
154 Branch
Tracking Status
firefox154 --- fixed

People

(Reporter: anba, Assigned: anba)

References

(Blocks 1 open bug)

Details

Attachments

(11 external files)

  • Support negative and unsigned modes for LDivPowTwoI and LModPowTwoI.
  • Implement LDivConstantI and LModConstantI (also unsigned and 64-bit versions).
  • Implement LDivPowTwoI64 and LModPowTwoI64.

Also see bug 1998457 for 64-bit division with constants on x64/arm64.

Fixes:

  • Add let to avoid creating global variables.
  • Fix argument order for assertEq.
  • And modernise some code.

Add codegenTestShared_adhoc to avoid code duplication.

Used in part 10 when "codegen-riscv64-test.js" gets added.

The instruction decoder already emits the instruction bits.

Necessary for part 10 when checking the disassembly.

Update implementation to match the ARM64 code.

Update implementation to match the ARM64 code.

Implementation based on the x86-shared and arm64 code.

Implementation based on the x86-shared and arm64 code.

Tests copied from "binop-divrem-with-constant-arm64-ion-codegen.js" and then updated
for riscv64.

LModMaskI is no longer needed when LModConstantI is supported.

(module
  (func (export "f") (param i32) (result i32)
    (i32.rem_s (local.get 0) (i32.const 3))))

Was compiled to:

  sext.w    s1, a0
  sext.w    t2, s1
  mv        t1, t2
  mv        a0, zero
  blt       t1, zero, 12 -> L_negative
  li        t0, 1
  j         12 -> L_head
L_negative:
  li        t0, -1
  negw      t1, t1
L_head:
  andi      t4, t1, 0x3
  addw      a0, a0, t4
  addiw     t4, a0, -3
  blt       t4, zero, 8 -> L_sum_signed
  mv        a0, t4
L_sum_signed:
  srliw     t1, t1, 2
  bne       t1, zero, -24 -> L_head
  bge       t0, zero, 8 -> L_done
  negw      a0, a0
L_done:

And is now compiled to the branchless code:

sext.w    t1, a0
sext.w    t0, t1
lui       t4, 0x55555
addiw     t4, t4, 1366
mul       a0, t0, t4
srli      a0, a0, 32
sraiw     t4, t0, 31
subw      a0, a0, t4
sh1add    a0, a0, a0
sext.w    a0, a0
subw      a0, t0, a0
Pushed by andre.bargull@gmail.com: https://github.com/mozilla-firefox/firefox/commit/c769f6b5ccf6 https://hg.mozilla.org/integration/autoland/rev/0c0d2d932610 Part 1: Fix various issues in adhoc-multiplatform-test. r=jandem https://github.com/mozilla-firefox/firefox/commit/dff64c4edad0 https://hg.mozilla.org/integration/autoland/rev/7faea97ce670 Part 2: Add codegenTestShared_adhoc. r=jandem https://github.com/mozilla-firefox/firefox/commit/506a916fe05f https://hg.mozilla.org/integration/autoland/rev/a8901b969286 Part 3: Don't emit instruction bits twice for riscv64 Disassemble. r=jandem https://github.com/mozilla-firefox/firefox/commit/082e2a85bc85 https://hg.mozilla.org/integration/autoland/rev/cdb9c6e53b6a Part 4: Support negative and unsigned modes for LDivPowTwoI. r=jandem https://github.com/mozilla-firefox/firefox/commit/915d11c69774 https://hg.mozilla.org/integration/autoland/rev/93a8b8660a04 Part 5: Support negative and unsigned modes for LModPowTwoI. r=jandem https://github.com/mozilla-firefox/firefox/commit/f8ea0a803866 https://hg.mozilla.org/integration/autoland/rev/f715a4bf1ed7 Part 6: Implement LDivConstantI and LModConstantI for riscv64. r=jandem https://github.com/mozilla-firefox/firefox/commit/615ca5c55cf6 https://hg.mozilla.org/integration/autoland/rev/50d1233f8a4b Part 7: Implement LUDivConstant and LUModConstant for riscv64. r=jandem https://github.com/mozilla-firefox/firefox/commit/abc144ab51aa https://hg.mozilla.org/integration/autoland/rev/76920a6ee335 Part 8: Implement {Div,Mod,UDiv,UMod}ConstantI64 for riscv64. r=jandem https://github.com/mozilla-firefox/firefox/commit/12020ff2da3d https://hg.mozilla.org/integration/autoland/rev/3d482e8d164c Part 9: Implement LDivPowTwoI64 and LModPowTwoI64 for riscv64. r=jandem https://github.com/mozilla-firefox/firefox/commit/b2991732728c https://hg.mozilla.org/integration/autoland/rev/65702dfdf1a9 Part 10: Add tests. r=jandem https://github.com/mozilla-firefox/firefox/commit/234396e4a6c2 https://hg.mozilla.org/integration/autoland/rev/226feb018134 Part 11: Remove LModMaskI for riscv64. r=jandem
Regressions: 2052865
See Also: → 2056054
QA Whiteboard: [qa-triage-done-c155/b154]
See Also: → 2059293
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