2070557 - [riscv64] Elide redundant no-op `mv`-like instructions when applicable

Status: RESOLVED FIXED

(Core :: JavaScript Engine: JIT, task, P2)

Description

[Rong Bao [:csmantle]]

The riscv64 backend currently generates some no-op self-moves and other similar no-op instructions. We could try to eliminate them.

Recently, I have extended LoongLint with multi-architecture support, including riscv64. This optimization is discovered when evaluating LoongLint on riscv64 JITDumps produced by Octane. In total, this elides ~204 such instructions on this benchmark

Comment 1

[Rong Bao [:csmantle]]

Attachment: Bug 2070557 - [riscv64] Part 1: Switch to explicit addi in MacroAssembler::wasmMarkCallAsSlow(). r=jandem!

This helps later elision of self-moves.

Comment 2

[Rong Bao [:csmantle]]

Attachment: Bug 2070557 - [riscv64] Part 2: Introduce ma_mv for elidable moves. r=jandem!

This function will be used in later parts. Keep AssemblerRISCVI::mv()
intact since it corresponds to an actual RISC-V pseudo-instruction.

Comment 3

[Rong Bao [:csmantle]]

Attachment: Bug 2070557 - [riscv64] Part 3: Switch to ma_mv when applicable. r=jandem!

Per LoongLint for RISC-V, this eliminates 9 (out of 206) non-canonical
nops on Octane with codegen profile RVA23U64.

Comment 4

[Rong Bao [:csmantle]]

Attachment: Bug 2070557 - [riscv64] Part 4: Optimize zero immediate cases in ma_add64(Register, Register, Imm64). r=jandem!

Per LoongLint for RISC-V, this further eliminates 91 (out of 206)
no-ops on Octane.

Comment 5

[Rong Bao [:csmantle]]

Attachment: Bug 2070557 - [riscv64] Part 5: Optimize zero immediate cases in ma_or(Register, Register, Imm64). r=jandem!

Per LoongLint for RISC-V, this further eliminates 106 (out of 206)
no-ops on Octane.

Comment 6

[Rong Bao [:csmantle]]

Attachment: Bug 2070557 - [riscv64] Part 6: Optimize zero immediate cases in ma_sub64(Register, Register, Imm64). r=jandem!

Comment 7

[Pulsebot]

Pushed by [e-mail]:
https://github.com/mozilla-firefox/firefox/commit/3aea2ef8711f
https://hg.mozilla.org/integration/autoland/rev/43a089a7f75a
[riscv64] Part 1: Switch to explicit addi in MacroAssembler::wasmMarkCallAsSlow(). r=jandem
https://github.com/mozilla-firefox/firefox/commit/cf5bdde07db8
https://hg.mozilla.org/integration/autoland/rev/db02850efbba
[riscv64] Part 2: Introduce ma_mv for elidable moves. r=jandem
https://github.com/mozilla-firefox/firefox/commit/b58508c62abb
https://hg.mozilla.org/integration/autoland/rev/a5ba46738f1a
[riscv64] Part 3: Switch to ma_mv when applicable. r=jandem
https://github.com/mozilla-firefox/firefox/commit/9493753816b9
https://hg.mozilla.org/integration/autoland/rev/1f3f049aaade
[riscv64] Part 4: Optimize zero immediate cases in ma_add64(Register, Register, Imm64). r=jandem
https://github.com/mozilla-firefox/firefox/commit/0c14642b2ada
https://hg.mozilla.org/integration/autoland/rev/769a3b9b835f
[riscv64] Part 5: Optimize zero immediate cases in ma_or(Register, Register, Imm64). r=jandem
https://github.com/mozilla-firefox/firefox/commit/aa9130393f2e
https://hg.mozilla.org/integration/autoland/rev/702064d2d252
[riscv64] Part 6: Optimize zero immediate cases in ma_sub64(Register, Register, Imm64). r=jandem

Comment 8

[amarc]

https://hg.mozilla.org/mozilla-central/rev/43a089a7f75a
https://hg.mozilla.org/mozilla-central/rev/db02850efbba
https://hg.mozilla.org/mozilla-central/rev/a5ba46738f1a
https://hg.mozilla.org/mozilla-central/rev/1f3f049aaade
https://hg.mozilla.org/mozilla-central/rev/769a3b9b835f
https://hg.mozilla.org/mozilla-central/rev/702064d2d252