411170 - TT: add SSE2 support for x86 targets

Status: VERIFIED FIXED

(Tamarin Graveyard :: Virtual Machine, defect)

Description

[Edwin Smith]

tamarin-central has SSE2 support but tamarin-tracing doesn't. for direct performance comparisons we should add SSE2 support.

* use SSE2 registers to hold floating point values or quadword sized values (Box)
* use SSE2 operations when we can fit operands into SSE2 registers (any int operation, or *SD for scalar double ops)
* handle FPU->SSE moves when necessary (fmod, etc return result in FPU ST(0)) - does MOVQ do this?

SSE code is conditional on whether the cpu has SSE2 support (flag is already there).

Comment 1

[Edwin Smith]

Attachment: basic SSE2 support for floating point operations

TODO:
* add LIR_u2d
* heuristic for using x87 anyway since X87->XMM moves are expensive

preliminary results

                                X87     SSE
prime4                          125     94
boidsHeadless                   3031    3062
boidshackHeadless               1344    1312
DrawGridHeadless                2047    2063
access-binary-trees             1123    1124
access-fannkuch                 546     562
access-nbody                    234     219
access-nsieve                   765     764
bitops-3bit-bits-in-byte        31      31
bitops-bits-in-byte             93      94
bitops-bitwise-and              405     405
bitops-nsieve-bits              188     187
crypto-md5                      4104    4103
crypto-sha1                     1419    1420
math-cordic                     125     125
math-partial-sums               327     327
math-spectral-norm              157     109
s3d-cube                        1248    1264
s3d-morph                       125     125
s3d-raytrace                    1529    1529
string-fasta                    406     406
controlflow-recursive           1186    1185

Comment 2

[Edwin Smith]

adding u2d is no longer in scope of this bug, created 412299 for LIR_u2d

Comment 3

[Edwin Smith]

Attachment: hg bundle of change merged with tip (not yet sanitized)

Comment 4

[Rick Reitmaier]

Comment on attachment 296629 [details] [diff] [review]
basic SSE2 support for floating point operations

Assembler.cpp:588 did you mean '&' not '&&' 
Assembler.cpp:797 ucomisd(r,r) doesn't appear to set the flags, is this ok.

Comment 5

[Rick Reitmaier]

Comment on attachment 297009 [details]
hg bundle of change merged with tip (not yet sanitized)

good

Comment 6

[Edwin Smith]

(In reply to comment #4)
> (From update of attachment 296629 [details] [diff] [review])
> Assembler.cpp:588 did you mean '&' not '&&' 

yes i did, will fix.  (although both cases will assert anyway)

> Assembler.cpp:797 ucomisd(r,r) doesn't appear to set the flags, is this ok.

ucomisd() sets the condition codes.  callers of asm_fcmp() test for P or NP (parity bit only).  ucomisd only sets P when x != x, ie x is NaN, which is what we want.

Comment 7

[Edwin Smith]

pushed
http://hg.mozilla.org/tamarin-tracing/?rev/f8d0a6a31700