Nanojit currently offers 8-bit and 16-bit load operations (ldcb and ldcs) that zero-extend, but no equivalent with sign-extend. We can simulate with the existing instructions + shifts, but since pretty much all interesting processors provide a single instruction to do this directly, it would be vastly more efficient to include this as a nanojit primitive.
Scope creep: additionally, it really needs to provide volatile versions of the existing 8/18 load operations, since not all uses are likely to be CSE-able.
Prototype patch for this is included in a patch for bug 527083.
fixed as part of https://bugzilla.mozilla.org/show_bug.cgi?id=527083
Status: NEW → RESOLVED
Last Resolved: 9 years ago
Resolution: --- → FIXED
Status: RESOLVED → VERIFIED
Resolution: FIXED → DUPLICATE
Duplicate of bug: 527083
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