Currently we allocate an extra register for JSOP_MUL if one operand is constant. We do this because (quote) "not all CPUs have multiplication on immediates" GCC just generates a 3-operand IMUL instruction, and the x86, ARM and Sparc assemblers already support this (the ARM implementation uses a scratch register).
Created attachment 559675 [details] [diff] [review] Patch
Created attachment 559676 [details] [diff] [review] Patch
Comment on attachment 559676 [details] [diff] [review] Patch Yeah, differences in the supported instruction set should be abstracted away by the assembler as much as possible (see also: AbsoluteAddress on x86 vs. x64).
Attachment #559676 - Flags: review?(bhackett1024) → review+
Target Milestone: --- → mozilla9
Status: ASSIGNED → RESOLVED
Last Resolved: 7 years ago
Resolution: --- → FIXED
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