Currently we allocate an extra register for JSOP_MUL if one operand is constant. We do this because (quote) "not all CPUs have multiplication on immediates"
GCC just generates a 3-operand IMUL instruction, and the x86, ARM and Sparc assemblers already support this (the ARM implementation uses a scratch register).
Created attachment 559675 [details] [diff] [review]
Created attachment 559676 [details] [diff] [review]
Comment on attachment 559676 [details] [diff] [review]
Yeah, differences in the supported instruction set should be abstracted away by the assembler as much as possible (see also: AbsoluteAddress on x86 vs. x64).