Created attachment 646064 [details] [diff] [review] /home/mrosenberg/patches/fusedInsts-r0.patch The basic idea is on ARM most of the ALU based instructions can take a (limited) integer, a register *or* a register shifted by some amount! For the most part, we only use the first two modes, but by analyzing the MIR, we can generate add r0, r1, r2 lsl #4 rather than using two instructions, and giving the register allocator more work. This patche is quite thoroughly hacked together, and probably needs some architectural fixes.
Whiteboard: [js:t] → [ion:t]
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