962263 - Add compiler support for packed overlapping floating point registers

Status: NEW

(Core :: JavaScript Engine: JIT, defect, P5)

Description

[Douglas Crosher [:dougc]]

The ARMv7 has packed and overlapping views of the floating point registers.

For example, the 128 bit SIMD register Q0 shares state with the 64 bit double float registers D0 and D1, and with the float32 registers S0 to S3 - in a similar manner to JS typed array views of an array buffer.

This is currently an issue for the float32 support, but is worked around by only using the even float32 registers.  But there are issues with hardfp ABI calls that require arguments to be passed in both even and odd float32 registers.  It might also help improve performance to make all 32 float32 register available for use.

Experimental SIMD support needs to allocate quad-word sided blocks of float registers.  It does not appear practical to only use every second double float register and one-in-four float32 registers, so some new infrastructure will be needed.

One approach would be to add separate floating point register allocation classes, each with an element-size, element-alignment, and the number of elements:

On SIMD capable hardware:
float32   : element-size 1, element-alignment 1, number-of-elements 32
double    : element-size 2, element-alignment 2, number-of-elements 32
SIMD quad : element-size 4, element-alignment 4, number-of-elements 16

The register allocator would need to be extended to take the element size into account when considering conflicts.