Closed
Bug 1074509
Opened 10 years ago
Closed 10 years ago
SIMD: Implement NaN-correct greaterThan and greaterThanOrEqual for x86
Categories
(Core :: JavaScript Engine: JIT, defect)
Core
JavaScript Engine: JIT
Tracking
()
RESOLVED
FIXED
mozilla35
People
(Reporter: sunfish, Assigned: sunfish)
References
Details
Attachments
(1 file)
18.52 KB,
patch
|
bbouvier
:
review+
|
Details | Diff | Splinter Review |
The greaterThan and greaterThanOrEqual functions should return false when either operand is a NaN. To implement this on x86 without using copies, we must reverse the operands to form lessThan or lessThanOrEqual before register allocation, since these instructions are two-address.
Attachment #8497124 -
Flags: review?(benj)
Comment 1•10 years ago
|
||
Comment on attachment 8497124 [details] [diff] [review] simd-float32x4-gt-ge.patch Review of attachment 8497124 [details] [diff] [review]: ----------------------------------------------------------------- Thanks, looks good to me. I think this patch is based on the one in bug 1072368, so you might want to rebase it on trunk or to ask the other one for r?. ::: js/src/jit/MIR.h @@ +1608,5 @@ > + switch (operation()) { > + case greaterThan: operation_ = lessThan; break; > + case greaterThanOrEqual: operation_ = lessThanOrEqual; break; > + case lessThan: operation_ = greaterThan; break; > + case lessThanOrEqual: operation_ = greaterThanOrEqual; break; nit: trailing whitespace ::: js/src/jit/arm/Lowering-arm.h @@ +59,5 @@ > bool lowerForFPU(LInstructionHelper<1, 2, 0> *ins, MDefinition *mir, > MDefinition *lhs, MDefinition *rhs); > + > + bool lowerForCompIx4(LSimdBinaryCompIx4 *ins, MSimdBinaryComp *mir, > + MDefinition *lhs, MDefinition *rhs) { nit: { goes to the next line, here and below. ::: js/src/jit/mips/Lowering-mips.h @@ +59,5 @@ > bool lowerForFPU(LInstructionHelper<1, 2, 0> *ins, MDefinition *mir, > MDefinition *lhs, MDefinition *rhs); > + > + bool lowerForCompIx4(LSimdBinaryCompIx4 *ins, MSimdBinaryComp *mir, > + MDefinition *lhs, MDefinition *rhs) { nit: { goes to the next line, here and below. ::: js/src/jit/shared/CodeGenerator-x86-shared.cpp @@ +2396,5 @@ > > // scr := scr > lhs (i.e. lhs < rhs) > // Improve by doing custom lowering (rhs is tied to the output register) > masm.packedGreaterThanInt32x4(ToOperand(ins->lhs()), ScratchSimdReg); > + masm.moveAlignedInt32x4(ScratchSimdReg, lhs); This code seems to be based on bug 1072368's patch...
Attachment #8497124 -
Flags: review?(benj) → review+
Assignee | ||
Comment 2•10 years ago
|
||
Rebased, and nits addressed: https://hg.mozilla.org/integration/mozilla-inbound/rev/696baf50aabd
Comment 3•10 years ago
|
||
https://hg.mozilla.org/mozilla-central/rev/696baf50aabd
Status: NEW → RESOLVED
Closed: 10 years ago
Flags: in-testsuite+
Resolution: --- → FIXED
Target Milestone: --- → mozilla35
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Description
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