Threads: Support new fence instruction
Categories
(Core :: JavaScript: WebAssembly, enhancement, P3)
Tracking
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firefox70 | --- | fixed |
People
(Reporter: lth, Assigned: rhunt)
References
Details
Attachments
(1 file)
The Wasm CG meeting in A Coruña in June 2019 voted to add an atomics.fence instruction to the threads proposal, to guard against a compatibility problem that may appear once we add weaker atomics in the future. Issue here: https://github.com/WebAssembly/threads/issues/140
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Comment 1•5 years ago
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Comment 2•5 years ago
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We want to be sure to get this into ff70.
Updated•5 years ago
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Updated•5 years ago
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Comment 3•5 years ago
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I've got a first attempt at implementing this working here [1].
The actual semantics of the operation hook into MacroAssembler::memoryBarrier. I had to hook into GlobalValueNumbering a bit to make sure that MWasmFence wasn't discarded from not being used with Ion, and need to verify there's no other places that need to be updated as well. I confirmed from looking at 'codegen' spew that mfence is actually being emitted on x86-64.
There's also a really basic test attached. I'm not sure what a great testing plan looks like at this time.
[1] https://treeherder.mozilla.org/#/jobs?repo=try&revision=ee9af92ff683766c57f1dbfcb902a922b18b29fb
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Comment 5•5 years ago
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It shouldn't be necessary to futz with GVN, it should be enough to flag the MIR node as guarded, I think? (Call setGuard() from the constructor.) Curious to know more details.
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Comment 6•5 years ago
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(In reply to Lars T Hansen [:lth] from comment #5)
It shouldn't be necessary to futz with GVN, it should be enough to flag the MIR node as guarded, I think? (Call setGuard() from the constructor.) Curious to know more details.
Ah, that sounds better. It was late, and I wanted to get it working :) I'll try that out soon.
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Comment 7•5 years ago
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This commit implements the 'atomic.fence' Wasm instruction.
Issue: https://github.com/WebAssembly/threads/issues/140
Overview: https://github.com/WebAssembly/threads/pull/141
The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future
memory order immediate. The instruction is implemented by emitting a memoryBarrier
through the macro assembler.
Comment 9•5 years ago
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bugherder |
Description
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