Closed Bug 1639464 Opened 8 months ago Closed 8 months ago

Optimize SIMD v8x16.shuffle in Ion x86_64


(Core :: Javascript: WebAssembly, enhancement, P2)




Tracking Status
firefox78 --- fixed


(Reporter: lth, Assigned: lth)




(1 file)

The v8x16.shuffle opcode is a very general workhorse for wasm SIMD, performing byte shuffle and blend. The straightforward implementation is expensive, equivalent to at least a dozen simple instructions (CONST + PSHUFB + CONST + PSHUFB + POR on x86). In many cases, the patterns are simple and can be lowered to a small number of instructions. We should recognize a number of these patterns and lower to better code.

Implement some shuffle specializations in the MacroAssembler interface
(permutations, interleaves, concat-and-shift) and then add code to the
Ion x64 back-end to pattern match the shuffle masks and map as many
cases as we can to these specializations.

The pattern matcher is simple: it sorts instructions into buckets of
single-operand, single-operand-with-zero, and dual-operand, and then
matches patterns on the shuffle mask in a fixed order from what is
perceived as least expensive to most expensive. The matcher is
optimized for clarity, not for speed, since it will run very rarely.

The patterns I've chosen are inspired by the SSE instruction set, the
v8 code, and the SIMD.js code. More can be added; some TODO remarks
are left in the code to indicate this.

A simple test infrastructure is added and used to ensure that
optimizations are triggered (and not triggered) as expected.

Currently the pattern matcher is in x64-specific code, since we only
support x64. But it will move without any substantive changes into
x86-shared code when we add x86 support (bug 1637332), and it is
mostly platform-independent and can eventually move into shared code,
possibly with some platform hooks and some extensions, when we add
arm64 support.

The matcher can also be used to optimize baseline code, should we wish
to do that.

Memo to self: we don't have to use PALIGNR for byte shifting the vector; we have PSLLDQ and PSRLDQ for that case and can avoid generating a zero or futzing with operand order.

Blocks: 1639517
Attachment #9150404 - Attachment description: Bug 1639464 - wasm ion simd: optimize v8x16.shuffle. r?jseward → Bug 1639464 - wasm ion simd: optimize v8x16.shuffle. r=jseward
Pushed by
wasm ion simd: optimize v8x16.shuffle.  r=jseward
Closed: 8 months ago
Resolution: --- → FIXED
Target Milestone: --- → mozilla78
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