1690460 - [meta] SIMD instruction selection optimizations

Status: NEW

(Core :: JavaScript: WebAssembly, task, P3)

Description

[Lars T Hansen [:lth]]

Tracking bug for SIMD instruction selection optimizations.

There are many suggestions for desirable special cases of instruction selection on the SIMD tracker, and we also have an internal document with a few more suggestions. Here I mean instruction selection narrowly: better code generation for individual SIMD instructions or perhaps very small trees of such instructions, not overarching optimization concerns.

All platforms are fair game here.

Some optimization advice from the intel optimization manual:

• "Use PSHUFB if the alternative uses 5 or more instructions"
• Blend operations that use XMM0 are most natural if XMM0 is the result of a previous operation that creates the mask. (Ie Blend is a natural for bitselect but maybe not for shuffle?)
• Section 5.5 has various ideas for generating common constants with few instructions; the implication is it's faster than memory load. (Some benchmarking finds that this is not necessarily the case, and/or the differences are very slight, and/or it's specific to generating integer constants in the integer part of the ALU, and we're not yet where that makes a difference.)

Comment 1

[Yury Delendik (:yury)]

Bug 1691490 adds i64x2.{gt,lt,ge,le}_s instructions, and for SSE4.1 and below, code is not optimal. SSE4.2 and above provides better lowering, see https://github.com/WebAssembly/simd/pull/412