2042565 - Improve handling of three-operand instructions without AVX

Status: NEW

(Core :: JavaScript Engine: JIT, enhancement, P1)

Description

[Iain Ireland [:iain]]

The VEX prefix, introduced with AVX, is necessary to encode three-operand versions of many SIMD instructions. Without AVX, the output register must be the same as the first input, which we enforce here in the BaseAssembler.

Right now, our generic macroassembler has many operations (eg addInt8x16 or bitwiseAndSimd128) that provide a three-operand interface. On x86, however, they call directly into BaseAssembler code that will assert if lhs != dest if AVX is not available.

This is currently enforced for wasm SIMD by the lowering code for MWasmBinarySimd128, which uses defineReuseInput unless AVX is available. However, we would like to use SIMD instructions in other contexts: for example, bug 1929128. Given that these macro-assembler operations are defined in architecture-independent code, it's awkward that they have restrictions that only appear on one platform (and only with --no-avx). We should support this better.

I think the easiest way to fix this is to simply generate an extra move from lhs to dest before generating the instruction if AVX is unavailable and they don't already match. The first chips supporting AVX (Sandy Bridge / Bulldozer) were released in 2011; we should still support non-AVX hardware, but inserting one extra move on 15-year-old chips is not a big deal. Testing locally, the extra moves don't make a meaningful difference to performance anyway.

Comment 1

[Iain Ireland [:iain]]

Attachment: Bug 2042565: Improve non-AVX support in simple three-operand SIMD operations r=yury

Comment 2

[Iain Ireland [:iain]]

Attachment: Bug 2042565: Enable SIMD for SkipUntilBitInTable without AVX r=yury